VLSI DESIGN ENGINEERING

ACCEL now offers ASIC Design courses with CADENCE TOOLS

RTL Designer – Digital Design, Verilog, system Verilog, ASIC Synthesis and STA.

Verification Engineer – Digital Design, Verilog, System Verilog and specman

FPGA Design Engineer – Digital Design, Verilog, FPGA, Xilinx and Altera.

Eligibility: B.E/B.Tech (ECE/EEE/CSE) with First Class.

Register online or contact your nearest ACCEL Centre for

Entrance Test on 26th November 2008.

For enquiries contact 044 42082899, 9841599424

Train.vlsi@accelacademy.in,

www.accelitacademy.com